The present invention generally relates to a dynamic random access memory (DRAM) in a semiconductor memory device, and more particularly, to a structure of a diffusion layer in contact with a storage node of DRAM provided with a stacked capacitor.
Most of DRAM devices are provided with a plurality of memory cells each having one transistor and one capacitor. An amount of 10 the electric charges accumulated in the capacitor of the memory cell determines either one state of logic "low", i.e., "0" or logic "high", i.e., "1", which state is stored into the capacitor and then read out through the transistor. Here, the more the amount of the accumulated charges is, the better the sensing operation of information in the memory device is. Thus, to enhance the device performance, the capacitance of the capacitor should be made as large as possible. This is accomplished by increasing the plate area of the capacitor or decreasing the plate spacing thereof, under a given available dielectric constant of the dielectric. The decrease of the plate spacing of the capacitor, however, has itself the limit. Also the plate area thereof is minimized in proportional to the decrease of device area occupied by the high-density memory device. As a result, if the plane capacitor is employed in the high-density memory devices, the capacitance suitable for high-density memory device is not achieved. In attempt to solve this problem, the trench capacitor, in three-dimension, formed in a substrate, and the stacked capacitor, in three-dimension, formed on the substrate are contrived.
Referring to FIG. 1 illustrating the layout of the semiconductor memory device with a stacked capacitor, an active region 2 and a word line 4 are respectively extended in horizontal direction and vertical direction. A first and a second contact regions 6, 8 are disposed over the active region 2. A bit line 10 is extended in horizontal direction, with being contacted with the second contact region 8. Also a storage electrode region 12 is disposed over the active region 2, with being contacted with the first conducting region 6. A plate electrode region 14, wholly covering the storage electrode region 12, is disposed over the storage electrode region 12.
FIG. 2 illustrates the cross sectional view of the FIG. 1. A source and drain regions 16, 18, separated from each other by a channel region over the substrate, are formed in the substrate of a first conductivity type having first and second field oxide layers 21, 22. A gate, served as a word line, is disposed on a gate insulation layer 24, as an interlayer, covering the channel region. The top surface of the substrate except for the first and second contact regions 6, 8 is covered with an insulating layer 26. The bit line 10 of a metal film and the storage electrode 12 made of a first polysilicon layer are respectively in contact with the second contact region 8 and the first contact region 6. The plate electrode 14 made of a second polysilicon covers the whole storage electrode 12 formed on a dielectric layer 28. The MOS transistor of DRAM is constituted by the source and drain regions 16, 18 and the gate 4. The capacitor thereof is constituted by the storage electrode 12, the dielectric layer 28 and plate electrode 14.
When the density scale of the memory cells is not large enough and the tolerance for the process margin is large, the first contact region 6 is formed within the source region 16, as shown in FIG. 2. In case where the distance between the elements of memory cells, however, is decreased in proportional to the increase of the density of the memory cell, the distance between the one side of the first contact region 6 and the field oxide layer adjacent thereto is less than a micron. Thus, the mask process, in manufacturing the memory cell, requires a very critical alignment process. In the practical process for forming the high-density memory cell, however, the first contact region 6 may be formed outside of the source region because of the mis-align according to the decrease of the process margin.
FIG. 3 illustrates the cross sectional view of the conventional memory cell having an undesirable structure caused by the mis-alignment. As shown in FIG. 3, the mask pattern for forming the first contact region is shifted toward the first field oxide layer 21. The first contact region 6 intrudes part of the first field oxide layer 21. That is, part of the contact region positioned outside of the source region 16 comes in contact with the substrate 20 of the first conductivity type with a low concentration, to thereby form a second contact region of a relatively weak junction, in comparison with the junction between 10 the source region of a high concentration and the substrate. Through the second contact region, the current accumulated in the storage electrode comes to leak and to degrade the characteristic of the refresh operation. On the other hand, the .alpha. particles radiated from uranium and thorium contained in package material for use in seal of the memory chips, collide with the lattice in the substrate, to generate holes and electrons. The generated holes and electrons cause the data, injected into and stored in the storage region through the second contact region, to be inverted. This phenomenon is called soft error. The soft error rate increases with the minimization of the memory device, so that the reliability of the operation of the memory cell is reduced. Thus, the problems of leakage current and soft error shall be resolved in order to realize the high-density memory device having high reliability.